I can give you the VHDL version of that book

# FPGA Discussion

Well, bring it in next time and I will see if it is the kind that I can use. I do not even know if I should use VHDL or Verilog, both of which I am not familiar with. I assume the Xilinx tools can use either?

ISE and Vivado both allow Verilog and VHDL development. Verilog is kinda like C, VHDL is more like Ada. You can mix the two in a single project although there are case sensitivity issues.

Verilog has 4 values per bit - 0, 1, X and Z. VHDL has 9 values per bit. More possibilities, more complexity.

I believe the logic analyser project uses VHDL.

The book Derryn is offering is unusual in that the author wrote the same book twice, once in Verilog and again in VHDL. The same structure used used for each book, just different code.

I’m a pretty firm believer in saying it doesn’t matter which language you use in this case. I’ve never head good unbiased argument either way.

While they’re syntactically completely different, the real meat of the problem is in learning how to map ideas into efficient designs. Far more so than with computer programming languages.

Just using whatever everyone else is maybe the strongest reason.

The weekend started with wanting to add a button interface for another FPGA project. I had a 4x4 button matrix pad and a few hours to spare, after staring at, and re-writing the same code for far too long - now finally at the end of the weekend, a solution that gives numerical value for one of the 16 pins. Possibly a show-and-tell for Wednesday.

Hi I am new here!

Hi @Andrew, worked it out. My bad, on the OBUFT I took the T pin to be the enable pin, i.e. turn the driver on.

T actually means tri-state, i.e. turn the driver off.

UG615 (Spartan 6 Library Guide) pg. 220 makes it clear.

This explains the inversion.

Cheers,

SteveD

Hi all,

tonights discussion touched on VHDL v Verilog. One of the early topics was 4 level logic (Verilog) v 9 level logic (VHDL).

How can a digital signal have 4 or 9 values?

Firstly, both languages allow simulation, i.e. what if type situations. They also allow synthesis (creating actual circuits). In the real world digital logic **input** values are either 0 (low), 1 (high) or floating (undefined). **Output** values are either 0, 1 or tri-state (disconnected/floating).

Verilog has 4 logic values - 0, 1, Z (tri-state output) and X (undefined). X occurs during simulation when the value of an input has not yet been defined or when an output in tri-state mode (Z) is connected to an input.

During Verilog simulation 4 logic levels can yield some interesting, but logical, results. Consider a 2 input OR gate. If one input is 0 then the output is completely dependent on the other input. If its value is 1 then the output will be 1. If its value is either Z or X then the output will be X (undefined). Why? Because the simulator cannot determine the correct output value given the current inputs.

Let’s now consider a 2 input OR gate when one input is 1. What happens when the other input is Z or X? The answer is quite logical, the output is always 1. Took me by surprise the first time I encountered it.

As a second exercise consider a 2 input AND gate. When one input is logic 0, what should be the output value when the other other input is 0,1 X or Z? What happens when you repeat the exercise with one input set to 1?

Cheers,

SteveD