I too came home and read up on the 2A03. It got me interested enough to implement a very minimal triangle channel.
I think the system emulators are one of the better ‘hobby’ projects I’ve seen on FPGAs. Along with all the SDR things people are doing.
I’ll chuck in here a recommendation for those getting started, check out the nandland youtube channel. It obviously a work in progress, but he has some of the most clear and practical explanations of things like crossing clock domains that are super helpful to learn early on if you intend on interfacing within anything.
Well I’m lost for words, that’s just fantastic.
I’d like to say I’m making progress on my own demo, but, well, things are taking their time.
BTW, diagram is here: https://github.com/makehackvoid/fpga-sig/blob/master/2019_ricoh2A03/tri_channel_1.jpg
I had a stickybeak through, I won’t say it’s surprisingly simple, I will say that it’s much more refined than any of the messes I’ve ended up making, however.
Tonight Eyal, Rene and I hacked up a quick blink example for the QM Spartan 6 board.
you’ve mentioned building a logic analyser on several occasions.
I know of sump, and was considering the use of the PC side (client) of it.
I should look through my old projects and see if I still have any part of the (very) simple project I built somewhere in the mid 80’s. I think.
But more to the point, I still consider a logic analyzer to be a suitable first FPGA project, with the emphasis on the hardware (capture) part.
@eyal, the sump project consists of a pc client and a Spartan 6 based fpga sampler.
Whilst a logic analyser is a reasonable project, you have to admit, a bit like building a VGA interface or any of the other standard learning projects, there’s very good cheap logic analysers available off the shelf.
If fact unless you interface the SDRAM, you’d probably be better off hooking up the ChipScope IP (xilinx term, but Altera or Lattice have an equivalent.)
As an alternative with similar level of complexity, I reckon you could make a low spec/feature version of one of these https://www.joulescope.com/ Personally I think it’s just a matter of time before a cheap open source alternative comes out. I’d love to see a $20-30 design that you could have made by one of the PCB assembly services on-demand.
I have been playing with a Haasoscope based on the Altera Max 10, has been alot of fun as an O-scope but also does 8ch at 250MSPs logic analyzer through matplot for visualisation and command - being open-source so the implementation is all there, I can bring it along one wednesday.
@Harvs I hear you. I selected this project as a simple one for me to learn to use the tools and the language.
joulescope is still $800. I need to run a test that lasts a few months (my 2nd test is running now) and I am getting good results with the
INA226). I am also experimenting with the tiny
eZ430-F2013. It should run using less than 1mA (It measured 440uA when doing a busy wait) and has a 16-bit ADC so should cover 5uA-300mA which is all I need.
Yes, please bring it in.
I looked at this project before and thought the small recording depth is an issue. I use a humble Rigol DS1074Z and regularly take a single shot then spend time drilling into the detail.
Not sure where you’re starting from, suggest the book on Verilog by Pong Chu.
I can give you the VHDL version of that book
Well, bring it in next time and I will see if it is the kind that I can use. I do not even know if I should use VHDL or Verilog, both of which I am not familiar with. I assume the Xilinx tools can use either?
ISE and Vivado both allow Verilog and VHDL development. Verilog is kinda like C, VHDL is more like Ada. You can mix the two in a single project although there are case sensitivity issues.
Verilog has 4 values per bit - 0, 1, X and Z. VHDL has 9 values per bit. More possibilities, more complexity.
I believe the logic analyser project uses VHDL.
The book Derryn is offering is unusual in that the author wrote the same book twice, once in Verilog and again in VHDL. The same structure used used for each book, just different code.